1. Field of the Invention
The present invention relates to a method and apparatus for fabricating semiconductor devices, and more particularly relates to a wiring forming method of semiconductor devices using porous material with low dielectric constant as intermetallic dielectric and using copper as conductor material.
2. Description of the Related Prior Arts
With respect to a wiring forming method of semiconductor devices using material with low dielectric constant, xe2x80x9cShingaku Giho; TECHNICAL REPORT OF IEICE, ED2000-136, SDM2000-118, ICD2000-72(2000-08), pp. 87-92xe2x80x9d (reference 1) discloses the title xe2x80x9cTechnique for forming Cu dual damascene interconnects using low dielectric constant filmsxe2x80x9d. Further, as a cleaning technique, xe2x80x9cGijutsu Joho Kyokai Shuppan (issued on Dec. 27, 2000) pp. 295-305xe2x80x9d (reference 2) discloses the title xe2x80x9cNew material and process technique of the next generation of ULSI Interconnectxe2x80x9d. Furthermore, as a resist ashing technique, there is a technique disclosed in xe2x80x9cJapanese Published Unexamined Patent Application No. Hei 11-176818 (corresponding to U.S. Pat. No. 6,232,237) (references 3 and 4).
The present inventors have studied the following technique as a wiring forming method of semiconductor devices using material with low dielectric constant (hereinafter, called lowxe2x80x94k dielectric) and copper. The method will be explained in accordance with the process diagram of FIG. 2.
First, in (step 1), a dielectric barrier film (e.g., an SiN film) 4 is deposited by CVD on a sample (an initial structure) having a copper layer 3 buried into the stacked-structure of a low-k film 1 and a silicon oxide (TEOS) layer 2. In (step 2), a low-k film 5 is coated thereon. In (step 3), a mask material layer 6 (e.g., TEOS) is deposited thereon. In (step 4), a material of the same kind of the dielectric barrier film 4 is deposited thereon as a mask material layer 7. In (step 5), a photoresist 8 is coated thereon to pattern a hole structure in the photoresist 8. In (step 6), the mask material layer 7 is dry-etched with the photoresist 8 as a mask to form a hole structure in the mask material layer 7. In (step 7), the photoresist 8 is removed. In (step 8), a new photoresist 9 is coated to pattern a trench structure in the photoresist 9. In (step 9), the mask material layer 6 is dry-etched with the mask material layer 7 as a mask to form a hole structure in the mask material layer 6, thereby providing a hard-mask made of the mask material layer 6.
In (step 10), the mask material layer 7 is etched with the photoresist 9 as a mask to form a trench structure in the mask material layer 7, thereby providing a hard-mask made of the mask material layer 7. In (step 11), the low-k film 5 is subject to anisotropic dry etching with the mask material layer 6 as a mask to form a hole structure (a via hole) 10. In (step 12), the mask material layer 6 is dry-etched in a trench form with the mask material layer 7 as a mask. In this process, the photoresist 9 is removed at the same time.
In (step 13), the low-k film 5 is subject to anisotropic dry etching with the mask material layers 7 and 6 as a mask to form a trench-structure recess 11. In (step 14), the dielectric barrier film 4 is removed by dry etching with the hole structure (the via hole) 10 formed in the low-k film 5 as a mask opening to form a hole structure. At the same time, the mask material layer 7 of the same material of the dielectric barrier film 4 is removed by dry etching. In (step 15), to remove a polymer containing copper 12 deposited on the inner wall surface of the via hole 10 in the previous process, a fluorocarbon film 13 deposited on the inner wall surface of the trench-structure recess 11, and a copper degraded layer 14 formed on the surface of the copper layer 3, wet cleaning is performed using chemicals containing amine. In (step 16), a Taxe2x80x94TaN stacked film 15 is deposited by a sputtering method. In (step 17), a copper layer 16 is deposited by the sputtering method.
In (step 18), a copper film 17 is electrochemical deposited on the copper layer 16 deposited by sputtering in the previous process. In (step 19), excess portions of the copper layer 16, the copper film 17, and the Taxe2x80x94TaN stacked film 15 is removed by the CMP method (Chemical Mechanical Polishing). Finally, in (step 20), the wet cleaning is performed to obtain a wiring completion sample of the first layer. The processes 1 to 20 are performed repeatedly to form interconnect.
In a high speed device, it is essential to use an insulating film with very low dielectric constant less than 2.5. Such an insulating film is entirely porous, that is, a low-k film like a sponge. The insulating film easily trap chemicals by the wet cleaning process and cannot be easily dried. The chemicals trapping of the porous low-k film is the principal problem.
The wiring method illustrated in FIG. 2 using the porous low-k film has the wet cleaning process such as steps 15 and 20. The porous low-k film traps chemicals in the wet cleaning process, so that moisture remains in the film. For example, when the above-mentioned method in reference 3 is used to omit two wet cleaning processes, the fluorocarbon film 13 can be removed by an H2O plasma processing. However, since the polymer containing copper 12 cannot be removed, the polymer containing copper 12 remains and diffuses in the porous low-k film to deteriorate the electric property of the porous low-k film. In the method of reference 3, as compared with the process of FIG. 2, since adhesion of the TEOS layer 2 to the dielectric barrier film 4 is poor, the layers are easily removed by thermal treatment.
As described above, due to chemicals trapping property, remaining of the polymer containing copper or the copper degraded layer, and low adhesion, wiring forming of the porous low-k film and copper is very difficult currently.
Accordingly, to solve the foregoing problems, an object of the present invention is to provide a method and apparatus capable of forming good wiring of a porous low-k film and copper.
The present inventors have found that the wet cleaning of the previous process 15 has, in addition to three effects of (1) removal of the fluorocarbon film 13, (2) removal of the polymer containing copper 12, and (3) removal of the copper degraded layer 14, a fourth effect, (4) removal of fluorine included into the TEOS film in the etching process 14 by pure water cleaning in the wet cleaning process.
The above-mentioned method of reference 3 has no wet cleaning processes including the pure water cleaning at all, fluorine included into the TEOS film 6 in the etching process 14 remains. The present inventors have studied and found that the remaining fluorine lowers the adhesion of the dielectric barrier film 4 deposited on the TEOS film 6 in the second layer wiring forming process.
In other words, the present invention provides xe2x80x9cA method for fabricating semiconductor devices comprising at least: a first step for forming a first insulating material layer (a dielectric barrier film) on a sample; a second step for forming on the first insulating material layer a second insulating material layer (a porous low-k film) with a dielectric constant less than 2.5; a third step for patterning the second insulating material layer by a plasma etching method; a fourth step for depositing a metal film on the second insulating material layer by a sputtering method; a fifth step for forming a copper layer on the metal film; and a sixth step for removing an unnecessary portion of the copper layer by Chemical Mechanical Polishing, wherein all the processes from the third to the fourth step are performed under drying process conditions, and a pure water treatment for cleaning the sample with pure water is provided after the sixth stepxe2x80x9d.
All the processes from the third step for patterning the second insulating material layer by a plasma etching method to the fourth step for depositing a metal film on the second insulating material layer by a sputtering method are performed under dry process conditions. It is thus possible to prevent the second insulating material layer with low dielectric constant from trapping chemicals, and to avoid the above-mentioned problem of the deteriorated wiring property. The treatment for cleaning the sample with pure water is newly provided. It is also possible to eliminate the above-mentioned problem of the deteriorated adhesion due to the remaining fluorine into the TEOS film 6, thereby forming good wiring.
It is desirable not to expose the sample to the atmosphere during all the periods from the start of the third step for patterning the second insulating material layer by a plasma etching method to the end of the fourth step for depositing a metal film on the second insulating material layer by a sputtering method. It is possible to thoroughly prevent the second insulating material layer with low dielectric constant from trapping chemicals, thereby effectively avoiding the above-mentioned problem of the deteriorated wiring property.
After the third step and before the fourth step, it is desirable to include an etching process for removing the first insulating material layer (the dielectric barrier film) by etching by means of plasma of a mixed gas containing HF3 and Ar through an opening patterned in the second insulating material layer in the third step. The mixed gas plasma containing HF3 and Ar is used to reduce a bias electric power applied to the sample. The copper as the substrate can be prevented from being etched. The polymer containing copper will not be deposited. The effect of the HF3 gas can remove the fluorocarbon film.
In the process for plasma etching the first insulating material layer (the dielectric barrier film), the bias electric power per unit sample area applied to the sample is desirably below 0.16 W/cm2. It is thus possible to effectively prevent the copper as the substrate from being etched.
The processing pressure in the process for plasma etching the first insulating material layer (the dielectric barrier film) is desirably set to below 0.5 Pa. It is thus possible to prevent SiF or CF generated by etching of the dielectric barrier film (SiC film) from being deposited again on the sample as a foreign matter.
Immediately after the process for plasma etching the first insulating material layer (the dielectric barrier film), it is desirable to provide a process for subjecting to the sample an O2 or H2 plasma processing. In the plasma etching process immediately before the O2 or H2 plasma processing, the bottom surface of the processing hole (the via hole), that is, the fluorinated surface of the copper layer as the substrate can be recovered to a clean surface.
The present invention provides xe2x80x9cA plasma etching processing apparatus comprising: a sample table for placing a sample provided in a reduced pressure processing chamber; gas introduction means for introducing a processing gas into the reduced pressure processing chamber; exhaust means for exhausting the processing gas out of the reduced pressure processing chamber; and means for generating plasma of the introduced processing gas in the reduced pressure processing chamber, further comprising: magnetic field apply means for applying a magnetic field to the sample provided on the back surface of the sample; and voltage apply means for ON-OFF applying to the sample a negative DC voltage in which the OFF period of the ON-OFF application is below 10xe2x88x926 secondsxe2x80x9d.
The mutual effect of an electric field perpendicular to the sample surface formed by means of a negative DC voltage ON-OFF applied to the sample by the voltage apply means and a magnetic field formed in parallel with the sample surface by means of the magnetic field apply means can efficiently generate plasma of the etching gas introduced from the gas introduction mechanism. The negative voltage applied to the sample accelerates positive ions in the generated plasma which are then radiated into the sample surface to promote the etching reaction of the sample. Electrons are radiated into the sample surface during the apply OFF period of the apply negative voltage to prevent charging-up of the positive electric charge to the sample by the positive ion radiation. The charging-up prevention mechanism permits good etching of the insulating material such as the TEOS, SiN, SiC, or low-k film. Since a positive voltage is not applied to the sample, the positive ions are not accelerated and radiated into the inner wall surface of the processing chamber. Few foreign matters or metal contaminants are caused by cutting away the inner wall material of the processing chamber. The apply OFF period t of the apply negative voltage is set to below 10xe2x88x926 seconds which is sufficiently short. During the short apply OFF period t, the positive ions cannot reach the inner wall surface of the processing chamber. The inner wall material of the processing chamber will not cut away by ion bombardment.
The present invention provides a dry etching method comprising using the plasma etching processing apparatus to etch an insulating film deposited on a copper layer provided on a sample under the conditions of the negative DC voltage of below 200V. In this manner, the negative DC voltage applied to the sample is set to below 200V to etch the insulating film deposited on the copper layer. The copper layer 3 as the substrate will not be etched at all. The polymer containing copper will not deposited on the inner wall surface of the processing hole or processing trench.
The present invention provides xe2x80x9cAn apparatus for fabricating semiconductor devices comprising a sputtering processing chamber for depositing a metal film on a semiconductor sample by a sputtering method; and an etching processing chamber for etching an insulating film on the semiconductor sample by a dry etching method, further comprising: a plasma processing chamber for performing a plasma processing of the semiconductor device; and exhaust gas processing equipment capable of subjecting both combustible gas and combustion buck up gas to an exhaust gas process. In this manner, the exhaust gas processing equipment capable of subjecting both combustible gas and combustion buck up gas to an exhaust gas process is added to subject the semiconductor sample to a desired process using both combustible gas such as H2 and combustion buck up gas such as NF3 or O2 and to subject both combustible gas and combustion buck up gas exhausted from the processing chamber to an exhaust gas process. Here, the combustion buck up gas is a gas supporting or promoting the combustion of the combustible gas.
The apparatus for fabricating semiconductor devices is desirably provided with gas introduction means for introducing at least three gases of NF3, H2, and O2 into the processing chamber. The three-gas introduction means is provided to remove the fluorocarbon film by NF3 gas plasma. The oxidation effect by O2 gas plasma and the reduction effect by H2 gas are used to recover the contaminated (fluorinated) copper layer surface to a clean surface.
FIG. 1 shows a basic process diagram of a method for fabricating semiconductor devices according to the present invention. A new process of the present invention is largely different in the following points from the process shown in FIG. 2.
(1) First, in step 14 of FIG. 1, a mixed gas of NF3 and Ar is used to etch the dielectric barrier film 4. In this case, the bias electric power per unit area applied to the sample is below 0.16 W/cm2. Under the conditions, since the copper layer 3 is not etched at all, the polymer containing copper is not deposited on the inner wall surface of the via hole 10. The effect of the NF3 gas can effectively remove the fluorocarbon film on the inner wall surface of the trench 11 or the via hole 10 from the step 9 to 13.
In the process described above, the fluorocarbon film or the polymer containing copper will not deposited on the inner wall surface of the hole or trench. Since the degraded layer of the copper layer 3 surface is removed, the wet cleaning process after etching is unnecessary. Wet cleaning is not performed in step 16, and the process for depositing the next Taxe2x80x94TaN stacked film 15 can be done immediately. The problem of chemicals trapping of the wet cleaning will not be caused.
Unlike the above-mentioned method of reference 3, a wet cleaning process 21 is provided after a CMP process 20. In the wet cleaning after the CMP process, since the low-k film is not contacted directly with chemicals, the problem of chemicals trapping will not be caused. The remaining fluorine in the TEOS film 6 as the mask material layer can be removed by the pure water treatment in the wet cleaning process.
Other object, construction, and effect of the present invention will be naturally apparent in the detailed description with the following embodiments.